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LH1694
LH1694
DESCRIPTION
The LH1694 is a 256-output TFT-LCD gate driver IC.
256-output TFT-LCD Gate Driver IC
PIN CONNECTIONS
277-PIN TCP TOP VIEW
FEATURES
* Number of LCD drive outputs : 256 * LCD drive output sequence : Output shift direction can be selected OG1/OG256 or OG256/OG1 * Enable chain connection * Usable with both positive/negative power supplies * Output signal masking function * Input signal voltage : +2.7 to +3.6 V * LCD drive voltage : +16.0 to +42.0 V * Operating temperature : -30 to +85 C * Package : 277-pin TCP (Tape Carrier Package)
VDD VEE VSS VCC VLS GND SVIO R/L CKV OE1 OE2 OE3 SVOI GND TEST2 TEST1 VLS VCC VSS VEE VDD 277 276 275 274 273 272 271 270 269 268 267 266 265 264 263 262 261 260 259 258 257
1 OG1 2 OG2 3 OG3
CHIP SURFACE
254 OG254 255 OG255 256 OG256
NOTE :
Doesn't prescribe TCP outline.
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
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LH1694
PIN DESCRIPTION
PIN NO. 1 to 256 257, 277 258, 276 259, 275 260, 274 261, 273 264, 272 262, 263 265 266 to 268 269 270 271 SYMBOL OG1-OG256 VDD VEE VSS VCC VLS GND TEST1, TEST2 SVOI OE3-OE1 CKV R/L SVIO I/O O - - - - - - I I/O I I I I/O DESCRIPTION LCD drive output pins Power supply pins for LCD drive Power supply pins for LCD drive Power supply pins for logic system Power supply pins for logic system Power supply pins for logic input/output systems Ground pins for logic input IC test pins Vertical scanning start pulse input/output pin Input pins for output enable Vertical shift clock input pin Pin for selecting bi-directional shift register and setting cascade sequence Vertical scanning start pulse input/output pin
BLOCK DIAGRAM
TEST1 262 TEST2 263 SVOI 265 OE3 266 OE2 267 OE1 268 CKV 269 R/L 270 OUTPUT CIRCUIT SVIO 271 1 256 CONTROL LOGIC 1 LEVEL SHIFTER 256 1 BI-DIRECTIONAL SHIFT REGISTER 256
257 277 261 273 264 272 260 274 258 276 259 275 VDD VDD VLS VLS GND GND VCC VCC VEE VEE VSS VSS
1 OG1
256 OG256
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LH1694
FUNCTIONAL OPERATIONS OF EACH BLOCK
BLOCK Control Logic Bi-directional Shift Register Level Shifter Output Circuit FUNCTION Used to create signals necessary for mode selecting signal, cascade sequence setting signal and for operation of bi-directional shift register. Used as transfer circuit of LCD drive output start signal. It is possible to set LCD drive output sequence of OG1/OG256 direction or OG256/OG1 direction. Used as circuit which shifts LCD drive output signals transferred by bi-directional shift register to VDD-VEE level. Configured with output buffers to output VDD-VEE level.
INPUT/OUTPUT CIRCUITS
VLS
I
VSS
,
VLS VSS VLS VSS
To Internal Circuit
Level Shifter Internal Logic (VLS-GND/VCC-VSS) (VCC-VSS)
Applicable pins CKV, R/L, OE1-OE3, TEST1, TEST2
Fig. 1 Input Circuit
I
Output Signal O Output Control Signal
(VLS-GND)
Level Shifter (VLS-GND/VCC-VSS)
Fig. 2 Input/Output Circuit
3
To Internal Circuit
Applicable pins SVIO, SVOI
LH1694
VDD
O
From Internal Circuit (VDD-VEE)
VEE
Applicable pins OG1-OG256
Fig. 3 Output Circuit
FUNCTIONAL DESCRIPTION Pin Functions
SYMBOL VDD VLS GND VCC VEE VSS CKV FUNCTION Used as power supply pin for high level LCD drive. Used as power supply pin for input level shifters. Used as power supply pin for input level shifters. Used as power supply pin for logic system, normally connected to VSS + 5.0 V. Used as power supply pin for low level LCD drive. Used as logic system power supply pin. Used as vertical shift clock pulse input pin. Used as vertical scanning start pulse input/output pins. Data input/output pins for shift register. During input, data is read at the rising edge of the CKV. During output, data is output at the falling edge of the CKV. * When R/L = "H". SVOI is set to data output pin for next cascade, and SVIO is set to input pin for shift data. * When R/L = "L". SVOI is set to input pin for shift data, and SVIO is set to data output pin for next cascade. Used as input pin for selecting the shift direction of bi-directional shift register and for R/L setting the sequence of cascade connection. LCD drive outputs shift from OG1 to OG256 when set to "H". LCD drive outputs shift from OG256 to OG1 when set to "L". Input pins for output-enable. LCD drive output is set to "L", when OE1, OE2, and OE3 pins are set to "H", and it has no relation with clock input. Relationship between enable control and output pins; OE1 : OG1, OG4 OG250, OG253, OG256 OE2 : OG2, OG5 OG251, OG254 OE3 : OG3, OG6 OG252, OG255 Used as input pins for IC testing. Must be set to "H". Used as output pins for LCD drive output, and which output data at 2 levels. OG1-OG256 * Selecting data is output at VDD level . * Non-selecting data is output at VEE level .
SVIO SVOI
OE1 OE2 OE3
TEST1 TEST2
4
LH1694
Functional Operations
LH1694 can select the LCD drive output level (OG1 to OG256) by the set of the input signal (CKV, SVIO, SVOI, OE1, OE2, OE3). When the pin for selecting the bi-directional shift register (R/L) is set to "H", LCD drive outputs shift from OG1 to OG256, and when set to "L", LCD drive outputs shift from OG256 to OG1. OE1,OE2 and OE3 are signals for output-enable. Output pins output non-selecting data (VEE level) when OE1 to OE3 pins are set to "H" and it has no relation with input clock. While R/L = "H" input data from SVIO is read at the rising edge of shift clock (CKV), and outputs to LCD drive output pin OG1 at the width for one Example of Input/Output Timing (R/L = "H")
1 CKV SVIO (Input) OE1 OE2 OE3 OG1 OG2 OG3 OG4 OG5 OG6
* * * * *
cycle of shift clock. Next LCD drive output pins from OG2 to OG256 are sequentially shifted at the rising edge of the CKV for one cycle. Shift signal of OG256 is read at the falling edge of the clock signal, and the input data for the next cascade is output from the SVOI pin. While R/L = "L" input data from SVOI is read at the rising edge of shift clock (CKV), and outputs to LCD drive output pin OG256 at the width for one cycle of shift clock. Next LCD drive output pins from OG255 to OG1 are sequentially shifted at the rising edge of the CKV for one cycle. Shift signal of OG1 is read at the falling edge of the clock signal and the input data for the next cascade is output from the SVIO pin.
2
3
4
5
6
7
255
256
257
258
OG256 SVIO (Output)
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LH1694
PRECAUTIONS
Precautions when connecting or disconnecting the power supply This IC has a high-voltage LCD driver, so it may be permanently damaged by a high current which may flow if voltage is supplied to the LCD drive power supply while the logic system power supply is floating. Therefore, when connecting the power supply, observe the following sequence. Logic system power supply (VLS) or internal logic system power supply (VSS, VCC; VCC > VSS) / logic input / LCD drive power supply (VEE, VDD) It is possible to set voltage VEE to the same as VSS. When connecting the power supply when VEE = VSS, observe the following sequence and the recommended sequence figure shown below. Logic system power supply (VLS), internal logic system power supply (VSS, VCC; VCC > VSS) and low-level LCD drive power supply (VEE) / logic input / high-level LCD drive power supply (VDD) When disconnecting the power supply, follow the reverse sequence. Since the logic state of the internal circuit is unstable immediately after the logic system power is supplied, input CKV and SVIO (or SVOI) while initializing the internal circuit (minimum input clock number is 256 CKV).
VDD VLS Input 0V
VCC VSS, VEE
Input pin setting Input pins other than CKV, SVIO and SVOI must be set to "H" or "L" level.
Maximum ratings When connecting or disconnecting the power, this IC must be used within the range of the absolute maximum ratings.
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LH1694
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL VDD VLS Supply voltage VCC - VSS VEE - VSS VDD - VEE (VSS) Input voltage Storage temperature VIN TSTG APPLICABLE PINS VDD VLS VCC, VSS VEE, VSS VDD, VEE, VSS CKV, SVIO, SVOI, R/L, OE1-OE3, TEST1, TEST2 RATING -0.3 to +45.0 -0.3 to +7.0 -0.3 to +7.0 -0.3 to +45.0 -0.3 to +45.0 -0.3 to VLS + 0.3 -45 to +125 UNIT V V V V V V C 1, 2 NOTE
NOTES :
1. TA = +25 C 2. The maximum applicable voltage on any pin with respect to 0 V.
RECOMMENDED OPERATING CONDITIONS
PARAMETER SYMBOL VDD VLS VSS Supply voltage MIN. +5.5 +2.7 -20.0 TYP. +3.3 MAX. +35.0 +3.6 -5.0 VSS + 5.5 +11.0 +25.0 +42.0 VLS +85 UNIT V V V V V V V C 1 NOTE
VCC VSS + 4.5 VEE - VSS 0 VDD - VEE +16.0 (VSS)
Input voltage Operating temperature
VIN TOPR
0 -30
NOTE :
1. The applicable voltage on any pin with respect to 0 V.
Each power supply pin of LH1694 is set as shown below.
VDD VLS GND VCC VSS, VEE Internal Logic Input LCD Drive Output SVIO/SVOI Output
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LH1694
ELECTRICAL CHARACTERISTICS DC Characteristics
PARAMETER
(VLS = +2.7 to +3.6 V, VEE = VSS, TOPR = -30 to +85 C)
MIN. TYP. MAX. 0.2VLS 0.3VLS 0.8VLS 0.7VLS VEE + 0.4 VDD - 0.4 5.0 5.0 100 1.5 100 100 UNIT V V V V V V A A A mA A A 1 NOTE
SYMBOL CONDITIONS APPLICABLE PINS VLS = 2.7 to 3.0 V Input "Low" voltage VIL VLS = 3.0 to 3.6 V CKV, SVIO, SVOI, VLS = 2.7 to 3.0 V OE1-OE3, R/L Input "High" voltage VIH VLS = 3.0 to 3.6 V Output "Low" voltage VOL IOL = 0.4 mA OG1-OG256 Output "High" voltage VOH IOH = -0.4 mA Input "Low" current Input "High" current IIL IIH IDD Supply current ILS ICC IEE VI = 0 V VI = VLS CKV, SVIO, SVOI, OE1-OE3, R/L
2
NOTES :
1. All input pins : 3.3 V 2. CKV : Frequency = 31 kHz, "L" period width tWL = 16.2 s SVIO : Frequency = 60 Hz OE1 to OE3 : 0 V Other input pins : 3.3 V All output pins are opened.
AC Characteristics
PARAMETER Clock frequency "H" clock pulse width "L" clock pulse width Clock rise time Clock fall time Data setup time Data hold time Pulse rise time Pulse fall time OE enable time Output transfer delay time 1 Output rise time Output fall time Output transfer delay time 2 Output transfer delay time 3
(VLS = +2.7 to +3.6 V, VEE = VSS, TOPR = -30 to +85 C)
APPLICABLE PINS MIN. 1.0 CKV 1.0 100 100 CKV, SVIO, SVOI SVIO, SVOI OE1-OE3 1.0 1.0 CL = 300 pF OG1-OG256 1.0 1.0 1.0 CL = 50 pF SVIO, SVOI 1.0 100 300 100 100 TYP. MAX. 100 UNIT kHz s s ns ns ns ns ns ns s s s s s s
SYMBOL CONDITIONS fCKV tCLVH tCKVL tRCKV tFCKV tSU tH tRSPV tFSPV tOEW tDO tR tF tDOE tDSV
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LH1694
Timing Chart
tCKVH CKV 50% 50% tCKVL 50% tSU 90% 50% 10% tH 90% 50% 10% tFSPV tDO tDO VDD 50% 50% fCKV 50% 10% tFCKV tRCKV 90% 90% 50% 10%
SVIO
tRSPV
OG1
VEE tDO tDO VDD
OG2-OG256
50%
50%
VEE
CKV tR 90% OG256 10%
50%
50%
tF VDD 90%
10% VEE tDSV tDSV 50%
SVIO
50%
tOEW OE1-OE3 50% 50%
tDOE
tDOE VDD
OG1-OG256
50%
50%
VEE
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LH1694F
Film center Device center
PACKAGE
SVIO
COM3
COM4
COM4
R/L
GND
CKV
OE3
OE2
OE1
SVOI VCC VSS VEE VDD
TEST2
VLS (TEST1)
COM1 VLS GND 18.00.7 16.8 (SL) 16.8 (SL) [30.0 (E.L.)] 29.80.05(Holes) 28.0 (SL) 1.420.05 13.85 (SR) P1.00 x (26 - 1) = 25.00.04 W0.400.02 13.85 (SR) 0.9 (SL) VDD VCC VEE VSS 48.1750.2 44.86 0.9 (SL)
COM1
COM2
O2.0 (Good device hole)
2.0 (SL) 0.400.02
1.420.05
2-R1.05 (SR) 20.4 MAX. (Resin area) 4.750.05 2-O1.5 (Cu hole)
7.00.7 [7.0 (E.L.)]
[8.0]
UPILEX is a trademark of UBE INDUSTRIES, LTD..
Sprocket center 5.4MAX. (Resin area) Chip center 2-O2.7 (Cu)
[4.0 (E.L.)] 4.2 (SR) 4.5 (SL) 5.0 (SL) 8.5 (SL)
[13.9 (E.L.)]
3.4 (SR)
3.5 (SL)
1.50.05(Hole)
10
P0.12 x (264 - 1) = 31.560.05 W0.0600.02 32.60.05 (Mark) 16.4 (SR) [34.0 (E.L.)] [35.8] OG254 OG255 OG256 DUMMY COM2 COM1 COM1 16.4 (SR)
5.40.05 [6.9 (E.L.)]
7.6 (SR)
2-O1.9 (PI)
[3.5TYP. (3.2MIN.)]
0.600.02 0.400.02
0.2MAX. Pattern side
0.75MAX. Backside
1.1MAX. Total COM4 COM4 COM3 DUMMY OG1 OG2 OG3
PACKAGES FOR LCD DRIVERS
0.600.02
0.400.02
o Tape Specification
Tape width Tape type Perforation pitch 48 mm Super wide 4 pitches
o Tape Material
Substrate Adhesive Cu foil [thickness] Solder resist UPILEX S75 E type VLP 25 m Epoxy resin (Unit : mm)
[0.5]

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